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7.1.4 Basic Operating Mode Timing
The following paragraphs depict Atmel AT86RF232 state transitions and their timing
properties. Timing figures are explained in Table 7-1 , Table 7-2 , and Section 12.4 .
7.1.4.1 Power-on Procedure
The power-on procedure to P_ON state is shown in Figure 7-3 .
Figure 7-3. Power-on Procedure to P_ON State.
Event
State
Block
Time
0
100
V DD on
P_ON
XOSC, DVREG
t TR1
400
CLKM on
Time [μs]
When the external supply voltage (V DD ) is first supplied to the AT86RF232, the radio
transceiver enables the crystal oscillator (XOSC) and the internal 1.8V voltage regulator
for the digital domain (DVREG). After t TR1 = 330μs (typ.), the master clock signal is
available at pin 17 (CLKM) at default rate of 1MHz. As soon as CLKM is available the
SPI is enabled and can be used to control the transceiver. As long as no state change
towards state TRX_OFF is performed, the radio transceiver remains in P_ON state.
7.1.4.2 Wake-up Procedure
The wake-up procedure from SLEEP state is shown in Figure 7-4 .
Figure 7-4. Wake-up Procedure from SLEEP State.
0
200
Time [ μ s]
Event
State
Block
Time
SLEEP
SLP_TR = L
XOSC, DVREG
t TR2
CLKM on
IRQ_4 (AWAKE_END)
TRX_OFF
FTN XOSC, DVREG
The radio transceiver ’ s SLEEP state is left by releasing SLP_TR pin to logic low. This
restarts the XOSC and DVREG. After t TR2 = 210μs (typ.) the radio transceiver enters
TRX_OFF state. The internal clock signal is available and provided to pin 17 (CLKM), if
CLKM was enabled.
This procedure is similar to the Power-on Procedure. However the radio transceiver
automatically proceeds to the TRX_OFF state. During this, transition the filter-tuning
network (FTN) calibration is performed. Entering TRX_OFF state is signaled by
IRQ_4 (AWAKE_END), if this interrupt was enabled by the appropriate mask register
bit.
36
AT86RF232
8321A – MCU Wireless – 10/11
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